1. Field of the Invention
The present invention relates to a wiring substrate provided with a semiconductor integrated circuit chip connected to a mother board, which has high connecting reliability and light load in manufacturing steps. The invention also relates to a method of manufacturing a wiring substrate, and a semiconductor device using the wiring substrate.
2. Description of Related Art
There is disclosed a semiconductor integrated circuit device provided with a semiconductor integrated circuit chip, and an intermediate substrate electrically connected to the semiconductor integrated circuit chip, in which at least a portion of a wiring layer of the semiconductor integrated circuit chip is formed (see, for example, un-examined Japanese Patent Application Publication No. 2001-102479).
Specifically, this publication states:                There are provided with a semiconductor integrated circuit chip, and a substrate electrically connected to the semiconductor integrated circuit chip, in which at least a portion of a wiring layer of the semiconductor integrated circuit chip is formed.        A first layer wiring layer 21 is connected to a via 27 formed in a silicon substrate 20. The via 27 penetrates the silicon substrate 20, and functions as a connecting terminal with an LSI chip 1, for example.        A copper (Cu) film 49 having a thickness of 15 μm is formed as wiring material in the via.        An insulating film 45 consisting of a laminate layer of SiN/SiO2 is formed on the substrate 20 by CVD method. The insulating film 45 functions as a film for insulating the substrate 20 and the via 27 formed later in a via hole 43.        
In addition, the necessity of this semiconductor integrated circuit device is stated in detail in the description of prior art in this publication.
An example of a method of manufacturing a conventional semiconductor integrated circuit device will next be described with reference to FIGS. 6A to 6J, which illustrate a general manufacturing process of a silicon interposer of system-in-package (hereinafter referred to simply as “SiP”).
As shown in FIG. 6A, a silicon substrate 111 is prepared. As shown in FIG. 6B, a hole 112 having a depth of several hundreds μm and a diameter of several tens μm to several hundreds μm is formed in the silicon substrate 111 by photolithography technique, dry etching technique, and the like.
As shown in FIG. 6C, an insulating film 113, a barrier metal layer 114, a shield copper layer 115 are formed sequentially on the surface of the silicon substrate 111, including the inner surface of the hole 112. A copper plated layer 116 is then formed so as to bury the hole 112.
As shown in FIG. 6D, the excessive conductive films of the copper plated layer 116, the shield copper layer 115, and the barrier metal layer 114 on the surface of the silicon substrate 111 are removed by chemical mechanical polishing (hereinafter referred to as “CMP”), or the like. As a result, a connecting portion 117 composed of copper is formed at the inside of the hole 112 via the barrier metal layer 114 and the insulating film 113.
As shown in FIG. 6E, an insulating film 121 is formed on the surface of the silicon substrate 111, and a connecting hole 122 is opened in the insulating film 121 by photolithography technique and dry etching technique etc., and thereafter a wiring layer 123 is formed. The wiring layer 123 is used for joining to a semiconductor transistor circuit, which will not be described herein, and for forming a wiring circuit. The wiring layer 123 is obtainable by forming a wiring metal layer and patterning the wiring metal layer by photolithography technique and dry etching technique, etc. Subsequently, a protection insulting film 124 for coating the wiring layer 123 is formed.
As shown in FIG. 6F, the silicon substrate 111 is upside down, and adhered to a support board 132 with adhesive 131.
As shown in FIG. 6G, by grinding and polishing techniques, the bottom surface of the silicon substrate 111 is removed in a thickness of several hundreds μm, thereby to expose the copper connecting portion 117.
As shown in FIG. 6H, the bottom surface of the silicon substrate 111 except for the exposed connecting portion 117 is covered with an insulating film 141. For example, a polyimide film is used as the insulating film 141. Thereafter, an opening portion 142 is formed above the connecting portion 117 by photolithography technique.
As shown in FIG. 6I, a solder bump 151 connected to the connecting portion 117 is formed through the opening portion 142.
As shown in FIG. 6J, a silicon interposer 100 is separated individually by dicing, and joined to a mother board 200 with the solder bump 151.
The problem to be solved by the invention is that there is usually hole depth variation when forming a hole in a silicon substrate. This variation causes the disadvantage in the step of exposing the copper connecting portion 117, as described with reference to FIG. 6G. As shown in FIG. 7A, the connecting portion 117 is normally formed so as to project from the bottom surface of the silicon substrate 111. However, if the depth of the hole 112 is small, the copper connecting portion 117 may not be exposed from the bottom surface of the silicon substrate 111, as shown in FIG. 7B. If the amounts of back grinding and CMP (polishing) are increased to expose the connecting portion 117, as shown in FIG. 7C, the connecting portion 117 and the silicon substrate 111 are thinned due to the occurrences of erosion and dishing etc., which can cause the problem of undesired gaps, and the like.
The aim of forming a polyimide film before forming a bump is as follows. As shown in FIG. 6J, in joining the silicon interposer 100 to the mother board 200, if the forming position of the solder bump 151 deviates from the connecting portion 117, as shown in FIG. 8, the deformed solder bump 151 makes contact with the silicon substrate 111, thereby causing electrical continuity between the solder bump 151 and the silicon substrate 111 in some cases. Hence, to prevent the electrical continuity between the silicon substrate 111 and the connecting portion 117 due to the solder bump 151, it is necessary to form the insulating film 141 composed of the polyimide film, as described with reference to FIG. 6H. Therefore, the conventional technique suffers from the problem of increasing the number of manufacturing steps.